1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more specifically, to a method of manufacturing a semiconductor device capable of forming a grain size of a polysilicon layer small and uniform.
2. Discussion of Related Art
In recent years, as the level of the integration of the semiconductor device is increased, a device isolation film is formed by a self-aligned shallow trench isolation (SA-STI) process and a floating gate is therefore formed to have a stack structure in which first and second polysilicon layers are divided, in the process of fabricating a NAND flash memory device. In the above, the first polysilicon layer is formed using an undoped amorphous silicon layer. For this reason, a coarse grain size is formed due to a subsequent thermal process.
FIG. 1 is a TEM photograph showing that an amorphous silicon layer is crystallized by a thermal process.
Referring to FIG. 1, an approximate grain size is over about 200 nm by minimum. This size is more than twice the gate critical dimension. The grain boundary does not exist in a specific cell 1 and the grain boundary exists in a specific cell (in worse case, twin grain boundary). As such, as the grain size becomes large, variation in the program/erase threshold voltage of the flash memory cells whose operating principle is based on FN tunneling becomes great. For this reason, the erase speed of a specific cell whose grain boundary is relatively dense becomes faster than a common cell, thus becoming an over-erased cell. Such conditions are caused by reduction in the potential barrier height or electron trap due to the concentration of phosphorus that is relatively excessive in an oxide valley existing in the grain boundary region.